In many data communication applications, serializer and de-serializer (SERDES) devices facilitate the transmission of parallel data between two points across a serial link. Data at one point is converted from parallel data to serial data and transmitted through a communications channel to the second point where it received and converted from serial data to parallel data.
At high data rates, frequency-dependent signal loss occurring from the communications channel (the signal path between the two end points of a serial link), as well as signal dispersion and distortion, can occur. Ideally, without noise, jitter, and other loss and dispersion effects, a data eye at the receiver will exhibit a relatively ideal shape. In practice, the shape of the data eye changes with noise, jitter, other loss and dispersion effects, and with temperature and voltage variations. As such, the communications channel, whether wired, optical, or wireless, acts as a filter and might be modeled in the frequency domain with a transfer function. Correction for frequency dependent losses of the communications channel, and other forms of signal degradation, often requires signal equalization of the signal at a receiver.
Equalization through use of one or more equalizers compensates for the signal degradation to improve communication quality. Equalization may also be employed at the transmit side to pre-condition the signal. Equalization, a form of filtering, generally requires some estimate of the transfer function of the channel to set its filter parameters. However, in many cases, the specific frequency-dependent signal degradation characteristics of a communications channel are unknown, and often vary with time. In such cases, an equalizer with adaptive setting of parameters providing sufficient adjustable range might be employed to mitigate the signal degradation of the signal transmitted through the communications channel. Equalization might be through a front-end equalizer, a feedback equalizer, or some combination of both. The shape of the data eye also changes due to equalization applied to input signal of the receiver. In some systems, equalization applied by a transmitter's equalizer further alters the shape of the eye from the ideal.
If an analog equalizer is employed in the analog front-end (AFE), the data eye-operating margin improves. However, better performance might be achieved through use of a Decision Feedback Equalizer (DFE) in combination with an equalizer in the AFE. Classical DFE equalization cancels a significant amount of intersymbol interference (ISI) and opens up the vertical and horizontal data eye opening. In SERDES communication channels, DFE filtering is employed to cancel post-cursor ISI in the equalized channel's pulse response by subtracting the output of the DFE from an input signal. DFE filters include a number of taps, the number of which determines how well the post-cursor ISI might be cancelled by subtracting the output of the DFE from the input signal. The longer the filter length (i.e., the more filter taps), the more ISI terms might be cancelled, but at the expense of increasing DFE filter complexity and power consumption. Typically, the DFE coefficients are automatically adjusted with adaptive algorithms such as least mean square (LMS). In high speed applications the data path equalization components are most often implemented as analog, transistor level circuits and the adaptation is implemented as digital blocks.
An alternative approach implements only an analog to digital converter (ADC) in the AFE, and all other processing of the received signal is implemented fully in the digital domain. Such a Digital Signal Processing (DSP) data path offers better reliability, testability and flexibility, but presents implementation challenges due to lower clock speeds available in digital designs, leading to a need for greater parallelization of the DSP processing. One of the main equalization components, the DFE, is particularly difficult to parallelize due to its inherent feedback structure. One parallelization approach is to implement a fully “unrolled” DFE (the DFE is implemented without feedback paths), but this yields prohibitively large designs for practical applications, scaling exponentially with the number of tap coefficients or inversely with channel quality metrics.
In a fully digital SERDES receiver the equalization data path is fully implemented as digital blocks and typically follows a variable gain amplifier (VGA) and an ADC at the input. A typical digital data path comprises a feed forward equalizer (FFE), a DFE, and adaptation and calibration circuits. For a digital signal processor (DSP) implementation, the clock frequencies available in the digital data path are typically an order of magnitude, for example eight to sixteen times, slower than in case of the analog datapath equalization. To maintain the data rate through the receiver, the receiver data path is parallelized by the same factor (eight to sixteen times). DFE implementations do not parallelize efficiently due to the need of an immediate feedback from the previous bit to the next bit of processed data. To address this architectural feature in parallel implementations of the DFE, an unrolling technique may be used, but this yields prohibitively large designs for practical applications, scaling exponentially with the number of tap coefficients. For the typically needed six to ten tap DFE, the size/power cost is prohibitive.
In order to avoid the huge size/power penalty of a large parallelized DFE, a feed-forward equalizer (FFE) might be used in combination with a conventional DFE, with fewer taps, followed by a multi-stage pipelined decision feed-forward equalizer (DFFE), making the data path easier to parallelize and implement for very fast data rates. In order to cover all the significant ISI contributing positions in a given channel the processing delay of the DFFE might span several tens of signal symbol time intervals (samples) e.g., 40-50 samples. A parallel DFFE of this order of implementation having several taps on such a long delay line is relatively complex, and has high power consumption. Further, the samples are processed by the parallel DFFE stages using a set of coefficients that might change over time outside of the processing pipeline. The coefficients for any given set of samples being processed should not change and should “flow” with the processed samples as they make their way through the DFFE pipeline. However, such an implementation might be very complex and power intensive.